1. Field of the Invention
The present invention relates to a data communication device, a data communication system, and a data communication method for communications in the field of FA (factory automation) and the like.
2. Description of the Related Art
FIG. 21 illustrates the rough configuration of the conventional data communication system. In the configuration shown in FIG. 21, when a data carrier device 802 and a control device 801 perform data communications, four connection points are provided for each of a power supply VIN, a ground GND, a clock signal CLK, and a data signal DATA.
In a system in which a control device and a data carrier device perform data communications, there is a configuration for downsizing the system with two connection points used for bi-directional data communications.
For example, Japanese Patent Application Laid-Open No. 2003-069653 as a Japanese Patent describes the configuration.
FIG. 22 only illustrates a data carrier device 900 in the configuration including the control device and a data carrier device capable of performing bi-directional data communication using two connection points described in Japanese Patent Application Laid-Open No. 2003-069653. Using the timing chart for the data carrier device 900 in FIG. 22 shown in FIG. 23, the operation of the data carrier device 900 shown in FIG. 22 is described below.
The data carrier device 900 has only two terminals, that is, a terminal A and a terminal B, and the two terminals perform data communications with the control device. The terminal A receives a pulse voltage VA having a constant duty ratio.
The pulse voltage VA has two high level (hereinafter referred to as an H level) values of a voltage amplitude, that is, V1 and V2, and a low level (hereinafter referred to as an L level) is ground (GND) potential. The other terminal B receives a pulse voltage VB having equal voltage amplitude and an opposite phase as compared with the pulse voltage VA input to the terminal A. In the data carrier device 900 in which the pulse voltages VA and VB are input, a clock generation circuit 901 generates a clock signal CLK synchronized to the frequency of the two pulse voltages VA and VB. A VA+VB circuit 902 rectifies the two pulse voltages VA and VB, and generates a constant voltage indicating the H level having two values of V1 and V2 and the L level of the GND potential of the voltage amplitude as shown in FIG. 23. An amplitude identification circuit 903 detects the differential voltage of the voltage amplitude of the H level, and generates a data signal DATA. The clock signal CLK and the data signal DATA are supplied to an internal circuit 904 of the data carrier device 900, and the data to be communicated is generated.
As a data communication unit from the data carrier device 900, the impedance is converted between the terminals A and B by, for example, establishing a short circuit in the terminals A and B, and detecting it by a control device. Thus, the data from the data carrier device 900 is received.
Another configuration for establishing bi-directional data communications using two connection points with a view to downsizing a system is described in, for example, Japanese Patent Application Laid-Open No. H06-069911.
FIG. 24 illustrates the configuration for realizing the bi-directional data communication using two connection points described in Japanese Patent Application Laid-Open No. H06-069911. With the configuration shown in FIG. 24, when data is transmitted from a master 1 to a slave 2 in a data transmission circuit for performing bi-directional data communication between the master 1 and the slave 2, the data to be transmitted is superposed on the direct current voltage and transmitted according to a voltage signal. On the other hand, when the data is transmitted from the slave 2 to the master 1, it is transmitted as a current signal by drawing a current through a constant current circuit from the potential difference existing between the circuits, thereby realizing full-duplex communications in a two-wire.
With the configuration shown in FIG. 24, each bit of the transmission data from the master 1 to the slave 2 has a rising edge and a falling edge, and the rise timing of each bit is different from each other's and associated with the logic “1” or “0”. Thus, the data is superposed on the clock signal and supplied to the slave 2, and the data from the slave 2 to the master 1 can be transmitted in synchronization with the clock signal. Furthermore, a clock signal line for transmission of a clock signal is added, and can be communicated in a clock synchronous system.
In addition, Japanese Patent Application Laid-Open No. H11-346147 describes a configuration in which a sudden entry into an ON or OFF state of an output transistor can be avoided, and an output waveform can be slowly changed in a circuit for ON/OFF control of a constant current circuit.
FIG. 25 illustrates the configuration in which an output waveform can be slowly changed in a circuit for ON/OFF control of a constant current circuit described in Japanese Patent Application Laid-Open No. H11-346147. The configuration shown in FIG. 25 refers to an open/drain through rate output circuit for controlling using two constant currents IrH and IrL the gate electrode of the Q0 of the N-channel output transistor in which a drain electrode is grounded and in which an load RL is connected between the Vdd power supply line and the source electrode.
If an input pulse signal Vin changes from the low level to the high level, it is inverted by the inverters I1 and I2, and the gates of a P channel transistor Q1 and an N channel transistor Q2 enter the low level. Therefore, the P channel transistor Q1 is placed in the ON state, the N channel transistor Q2 is placed in the OFF state, the input capacity of the output transistor Q0 is charged by the constant current IrH from a constant current source CS1, and it gradually becomes the high level, thereby placing the output transistor Q0 in the ON state. When the input pulse signal Vin changes from the high level to the low level, the P channel transistor Q1 enters the OFF state, and the N channel transistor Q2 enters the ON state. Then, the input capacity of the output transistor Q0 is discharged by the constant current IrL from a constant current source CS2, and it gradually enters the low level, thereby placing the output transistor Q0 in the OFF state. Therefore, by controlling the values of the constant currents IrH and IrL, the charge/discharge time of the output transistor Q0 to the input capacity can be changed, and the rise time or the fall time of potential Vgate of the gate electrode of the output transistor Q0 for the input pulse signal Vin can be controlled. Thus, the fall time or the rise time of the output voltage Vout can be controlled.
In the Japanese Patent Application Laid-Open No. 2004-363684 as a Japanese patent, the control device transmits an in-phase clock pulse as a first transmission signal, and an opposite-phase clock pulse as a second transmission signal. At this time, when the “H” pulse of the second transmission signal is modulated to advance by the time of td1 over the “L” pulse of the first transmission signal when the transmission data has the logic “1”, and advance by the time of td2 when the transmission data has the logic “0”. The data carrier device demodulates data by detecting the change in delay time of the second transmission signal using the clock extracted from the first transmission signal.
However, the above-mentioned conventional data carrier device has the following problems. First, the four connection points respectively provided for the devices for the power supply VIN, the ground GND, the clock signal CLK, and the data signal DATA as shown in FIG. 21 are not appropriate in downsizing the system because four connection points are required to perform data communications.
The data carrier device 900 shown in FIG. 22 can operate without problems when no phase difference is detected between the pulse voltage VA input to the terminal A and the pulse voltage VB input to the terminal B. However, when there is phase difference, there occurs a period in which both of the two pulse voltages VA and VB are placed in the L level or the H level. Therefore, there arises a period in which electric power is not supplied to the data carrier device 900. As a result, there is the problem that the data carrier device 900 cannot be stably operated. In the actual configuration of the system, there often occurs a delay in an internal circuit between the timing of outputting a pulse voltage VA and the timing of outputting a pulse voltage VB in the control device. Also, there often occurs a difference in impedance caused by a resistance value, a parasitic capacity, etc. in the wiring from the control device to the terminal A and to the terminal B of the data carrier device 900. Therefore, it is very difficult to completely suppress the phase difference between the pulse voltage VA input to the terminal A and the pulse voltage VB input to the terminal B.
With the configuration shown in FIG. 24, the data to be transmitted is superposed on the direct current voltage. Therefore, when the circuit of the slave 2 operates with the data-superposed voltage as a power supply voltage, the power supply voltage largely fluctuates, thereby causing the operation of the internal circuit of the slave 2 to be unstable. Therefore, it is difficult to perform stable data communication. When the circuit of the slave 2 does not use the data-superposed voltage as a power supply voltage, stable data communication can be performed, but another input terminal for supplying a power supply voltage for the operation of the circuit is required. As a result, the system becomes large and costly.
With the configuration shown in FIG. 25, the charge/discharge time of the output transistor to the input capacity is changed, and the rise time or the fall time of the potential of the gate electrode of the output transistor for the input pulse signal is controlled. However, the moment when the potential of the gate electrode of the output transistor becomes higher or lower than the threshold voltage for the output transistor to be placed in the ON state, the output transistor suddenly changes from the OFF state to the ON state, or from the ON state to the OFF state. Therefore, the fall time or the rise time of the output voltage indicates a sharp change, and the configuration is not satisfactory for a moderate change of an output waveform.